The zero-bias band diagram in figure 2 a is called flat band diagram. The formation of this band diagram can conceptually think of the equilibrium metal-semiconductor contact but is separated with a distance x0, the thickness of the oxide layer.
The Fermi level aligned between metal and semiconductor since it's specified in the property 8 above. Since there are no charge or electric field in the flat band MOS-C device, the inserted insulator can only have an effect in slightly lowering the energy barrier and there is no block charge diagram for flat band like figure in 2 b. The block charge diagram shows the charge density distribution inside the MOS structure. Like the energy band diagram, the X-axis represents the distance x in the cross-section view.
There are two horizontal Y-axis which represent the metal-oxides interface and oxide-semiconductor interfaces. The region above X-axis is the positive charge Q which is created by holes concentration, while the region below X-axis is the negative charge Q which is created by electrons concentration.
Other than the flat band in the MOS structure, as the d. Three different types of biasing regions with different shape of both energy band and corresponding block charge diagram occur and they are showed in figure 3, 4, 5 and 6 below for n-type semiconductors.
However, the types of biasing regions are also different from n-type and p-type semiconductor because of the different positions of the Fermi level as well as the doped charges. Since the focus is the mechanisms under biasing conditions, the p-type diagrams follow the same concepts but are not discussed here. One thing worth mentioning is that the Fermi level of semiconductor does not change when V G is applied. Therefore, the V G can be calculated as the equation 1 shown below, where q is the electric charge.
There are two limits: low frequency limit and high frequency limit. Their behaviors differ at inversion and inversion to transition regions but they converge at depletion, flat band and accumulation regions. In summary, different types of biasing region depend on the biasing voltage applying to the MOS-C devices. Also, different doping of the n-type semiconductor and p-type semiconductor affects the biasing regions.
Please include the marking of V T. Introduction The principals of forming MOS structure are similar to the metal-semiconductor MS contact structures, but the MOS structure is like a sandwich structure which have a thin layer of silicon oxides in the middle between metal and semiconductor Si layer.
The metallic gate should thick enough to be equipotential region, where every points has the same potential in the space, under a. The oxides layer in the middle should be a perfect insulator with zero current flowing through under all static biasing conditions. There should be no charge centers located on the oxide-semiconductor interface.
The semiconductor should be uniformly doped with donors or acceptors as p-type or n-type semiconductors. The semiconductor Si should be thick enough for charges to encounter a field free region Si bulk before reaching the back contact. The Ohmic contacts should be established on the backside of the MOS device. MOS-C is a one-dimensional structure with variables only related to the x-coordinate distance as the Figure 1 below.
This property can be omitted, but it is easier to help with the initial understanding of the static behavior in MOS devices. Effect of an applied bias Other than the flat band in the MOS structure, as the d. From the band diagram view, the applied bias lowers the Fermi level of the metal below the Fermi level of the semiconductor.
The Ec and Ev of the semiconductor also bend down following the principals of MS contact. The majority carriers for n-type semiconductors electrons are trapped on the interface between oxides-semiconductor shown on figure 3 a.
From the block charge diagram view, there are some positive charges accumulates on the metal gate because of the positive bias, the negatively excess electrons in the semiconductors are attracted toward the oxide-semiconductor interfaces shown in figure 3 b. Figure 3 Accumulation of n-type MOS devices a band diagram b block charge diagram. The second type of biasing region is depletion, where the concentration of the majority carriers has been depleted. From the band diagram view, the applied bias raises the Fermi level of the metal higher than the Fermi level of the semiconductor.
The negative slope bending up direction bending occurs for the semiconductor. Viewed 7k times. I don't understand the physical meaning behind this sentence from Sze: to accommodate the work function difference, the semiconductor bands bend I understand that the work functions are the the energies required to move an electron from the fermilevel to the vacuum.
Improve this question. The only thing that can allow that to happen is band bending and rearrangement of charge to equalize the work functions between the materials. I have added a figure above.
I naively would have thought that the vacuum level should be at a constant value, but it seems that is wrong. I just don't quite see what exactly is being aligned by th bending in b in comparison to a. So, the Fermi energies must come in to alignment or there will be net carrier movement.
Why does that imply band bending? Thank you for your patience! Show 5 more comments. Active Oldest Votes. Improve this answer. As I understood it, in the MOS, electrons cannot travel through the oxide - and how does a work function difference imply an electrical field physically?
How can I imagine that in terms of actual field-inducing charges? This happens, e. The diagram b shows the case that gate and semiconductor are in equilibrium, i. Then an internal potential difference has to build-up which corresponds to the difference of work functions as depicted.
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